Nirmal R. Saxena

Nirmal R.
Saxena joined Alliance Semiconductor in April 2003 and brings more than 20 years of management, technical, and research experience in the areas of - VLSI design & test, instruction and packet processing architectures, coding & information theory, and fault-tolerant computing.
Nirmal is responsible for the architecture definition, engineering management, and new product development.
In addition to his duties with Alliance, Nirmal is also a Consulting Professor in the Electrical Engineering Department at Stanford University and supervises graduate research.
Prior to joining Alliance, Nirmal was VP of Architecture at Chip Engines where he was responsible for the design and development of Resilient Packet Ring (RPR) controllers.
In his accomplished career, Nirmal has served in senior technical postions at Tiara Networks (now Tasman Networks), the Stanford Center for Reliable Computing, Silicon Graphics, HaL Computers, and Hewlett Packard.
Nirmal holds a BE degree from Osmania University, India; a MSEE degree from the University of Iowa; and a Ph.D.
EE degree from Stanford University.
Nirmal holds more than 10 patents and has published extensively in the IEEE Transactions.
Nirmal is Fellow of IEEE (2002) and was cited for his contributions to reliable computing.